Implementation Of Odd-Length Fir Filter Design In 3-Parallel Polyp Phase Using Brent-Kung Adder And Booth Multiplier For VLSI Applications

Abstract

Digital Signal Processing (DSP) plays a crucial role in various fields, including biomedical applications, as
well as voice and image processing. In DSP and signal analysis, digital filters are essential components. With
the advancement of VLSI (Very-Large-Scale Integration) technology, the number of processes required to
design digital filters has reduced, promoting the development of on-chip VLSI architectures for DSP
applications. In DSP, Finite Impulse Response (FIR) filters are characterized by a finite duration of the impulse
response, meaning they settle to zero after a specific period. This is in contrast to Infinite Impulse Response
(IIR) filters, which may exhibit continuous responses due to internal feedback. This paper explores the
implementation of a 3-parallel poly phase FIR filter of odd length, based on the FF Algorithm, utilizing
optimized adders and multipliers to replace traditional components. Specifically, the design uses two types of
multipliers Vedic and Booth multipliers and three types of adders Ripple Carry Adder, Carry Look-Ahead
Adder, and Brent-Kung Adder. The focus is on reducing circuit complexity by using a modified version of the
Brent-Kung Adder instead of the conventional one, thus improving circuit efficiency. The proposed design is
implemented using Xilinx and simulated in Model Sim software.