Design and Analysis of Approximate Multipliers using Approximate 4:2 Compressors

Abstract

Approximate computing techniques have emerged 
as a promising approach to enhance efficiency by 
sacrificing a bit of accuracy. Within this 
framework, approximate multipliers have gained 
significant attention for their ability to find a sweet 
spot between precision, performance, and power 
efficiency. One popular method for creating these 
multipliers involves using 4:2 approximate 
compressors, which act as efficient components in 
approximate arithmetic circuits. This paper 
introduces two different designs for 4:2 
approximate compressors, which are then utilized 
to deliberately decrease the accuracy of the 
multiplier while achieving substantial gains in 
power efficiency and speed. The effectiveness of 
these proposed designs has been confirmed through 
simulations 
using 
the 
Genus software, 
demonstrating a noteworthy 30% and 34% 
reduction in the required area and a 42% and 44% 
reduction in power consumption. Exact computing 
units aren't necessarily essential in applications 
like data mining and multimedia signal processing. 
They may be substituted with a similar item. 
Research into error tolerant applications using 
approximation computation is on the increase. 
These applications rely heavily on adders and 
multipliers. 
In 
digital 
signal 
processing, 
approximate complete adders are suggested at the 
transistor level. Partial product accumulation in 
multipliers is handled by their suggested full-adder 
design.