DESIGN OF MULTIPLY-ACCUMULATE UNIT WITH SELFERROR CORRECTION & ACCUMULATION MODULE

Abstract

In the realm of digital signal processing, the design of Multiply-Accumulate (MAC) units plays a
pivotal role in achieving high-performance computations. The MAC design finds application in various fields
such as digital signal processing, communications, and artificial intelligence, where MAC operations are
fundamental for efficient computation of convolutional neural networks, digital filters, and other signal
processing tasks. Currently, MAC units commonly rely on separate adders and multipliers, leading to increased
hardware complexity and power consumption. The existing systems often struggle to strike a balance between
speed and resource utilization. Traditional MAC designs entail redundant hardware due to the independent
implementation of adders and multipliers. Separate adders and multipliers contribute to higher power
consumption, limiting energy efficiency. The existing systems may face scalability challenges, especially when
aiming for high-performance computing, due to their architecture. This work introduces a novel approach to
MAC unit design by employing unified adders and multipliers, aiming to enhance both speed and resource
utilization. The proposed method integrates unified adders and multipliers, optimizing the MAC unit for
improved speed and efficiency. By leveraging a unified architecture, the design minimizes redundancy,
enhances resource utilization, and reduces power consumption.