MODELING AND VERIFICATION OF LOW POWER MAC UNIT

Abstract

In this paper, we present the design, modeling, and verification of a low power Multiply-Accumulate (MAC)
unit, which is a fundamental building block in digital signal processing and machine learning applications.
Emphasizing energy efficiency, we employ various low power design techniques while maintaining
performance and accuracy. The paper discusses the architecture, implementation details in System Verilog, and
the verification methodology, providing a comprehensive framework for developing power-efficient MAC units.