Low Power Viterbi Decoder Design Based On Reversible Logic Gates

Abstract

In 5G mobile terminals the Viterbi decoder 
consumes approximately one third of the power 
consumption of a basic band mobile transceiver. 
Viterbi decoders employed in digital wireless 
communications are complex and dissipate large 
power. In this project, to reduce the power 
consumption, and to increase the speed, an 
asynchronous technique that is delay insensitive 
null convention logic (NCL) for Viterbi decoder 
using dual rail signal is proposed. NCL reduces the 
dynamic power consumption in terms of reducing 
the switching activity and it also reduces the glitch 
power significantly, thereby achieving the lower 
power. 
The Viterbi decoder consists of branch metric unit, 
add compare, and select unit and the survivor path 
memory unit. Viterbi algorithm is an effective 
implementation of a discrete-time finite state 
Markov process perceived in memoryless noise and 
optimality can be achieved by following the 
maximum-likelihood criteria.