OPTIMIZING LAYOUT DESIGN AND SIMULATION OF CMOS MULTIPLEXER ACROSS VARIOUS TECHNOLOGIES

Abstract

The multiplexer circuit serves as a fundamental component across
various branches of Engineering. In the realm of VLSI research, the primary
aim is to streamline and downsize designs. This paper focuses on leveraging
CMOS logic to craft a 2-to-1 multiplexer, aiming for a more straightforward
and efficient circuit. Employing a range of design methodologies, the objective
is to reduce the footprint, complexity, and power consumption of the
multiplexer. The study delves into the analysis of 35nm technology.
Additionally, the paper evaluates the design processes to optimize the effective
area of the multiplexer.