A Partially Static High Frequency 18T Hybrid Topological Flip Flop Design for Low Power Application
Abstract
An extremely low power true 1 φ clocking flip-flop is proposed using eighteen transistors only. The flip-flop is a synchronous bistable element that stores single-bit information. To design this Master Slave (MS) type architecture, topological, logical, and adaptive coupling techniques are employed. The minimum number of transistors are maintained by using above techniques, which comprises of complementary pass transistor logic and static complementary MOS logic. It also offers low power, a low delay that speeds up the flip-flops, and low complexity by reducing the transistor count. The proposed circuit is implemented using Cadence Virtuoso and compared with the five other reported logic structures of flip-flops. This project proposes a novel 18-transistor (18T) hybrid topological flip-flop design tailored for low-power, high-frequency applications. By integrating partially static and dynamic circuit techniques, the flip-flop achieves enhanced power efficiency and reduced switching activities. The architecture employs a mix of static storage and dynamic clock gating to minimize power consumption during idle states, making it suitable for modern high-performance systems-on- chip (SoCs) operating in energy-constrained environments. This hybrid design is ideal for systems requiring both high-speed operations and low-energy footprints, making it highly applicable to portable and IoT devices.