Design and Analysis Of 32 Bit Alu Using Reversible Gates

Abstract

Research into low-power arithmetic logic unit
(ALU) designs has been prompted by the growing
need for computing that uses less energy.
According to Landauer's principle, reversible
computing provides a promising solution by
reducing information loss and energy dissipation.
In this paper, a 32-bit ALU with high
computational efficiency and low power
consumption is designed using reversible logic
gates. Optimized reversible gate structures,
including the Fredkin, Toffoli, Peres, and HNG
gates, are used in the implementation of the
suggested ALU architecture to carry out arithmetic
and logical operations with the least amount of
power consumption. Reversible full adders and
multiplexers are effectively integrated into the
design to carry out basic ALU operations while
guaranteeing garbage output and ancilla bit
minimization. The power consumption, delay,
quantum cost, and hardware complexity of the
suggested ALU are assessed.