THE ANALYSIS OF STOCHASTIC NUMBER GENERATOR USING HDL IMPLEMENTATION

Abstract

For stochastic computing (SC) circuits to be accurate and area-efficient, stochastic number
generators (SNGs) must be designed efficiently. SNGs based on linear feedback shift registers (LFSRs) are
widely used in SC. On the other hand, we suggest a novel design strategy to minimize the size of SNGs:
distributing among several SNGs a mix of negations and permutations of the output of a single LFSR. This
method produces SC circuits with improved accuracy by providing SNGs with least average SC correlation
(SCC) without requiring any extra hardware overhead... When a 10-bit LFSR is shared between two SNGs, our
method produces stochastic bit streams with an average SCC that is 50% lower than the prior state-of-the-art
work. The proposed design space for a ????-bit LFSR includes ????! × 2 ???? designs. Nevertheless, searching the entire
area for the design with the least SCC becomes unfeasible when ???? > 7. We offer an optimized search algorithm
to tackle this problem. When ???? < ????, our optimized search technique can locate a set of ???? distinct designs with
least SCC values. This solves the issue of looking through the whole design area and makes it possible to
explore design possibilities quickly.