A 12-BIT COLUMN-PARALLEL TWO-STEP SINGLE SLOPE ADC WITH A FOREGROUND CALIBRATION FOR CMOS IMAGE SENSORS

Abstract

A unique analog-to-digital converter (ADC) for high-speed CMOS image sensors that is 12-bit
column-parallel and two-step single-slope (SS). The small electronic device known as a CMOS image sensor, or
complementary metal-oxide-semiconductor image sensor, is essential to the capture of the pictures we see on
our digital cameras, cellphones, and other imaging devices. It serves as the "electronic eye" of these gadgets,
processing and displaying digital information from light.To reduce non-uniformity in column-level ADCs, a
novel correlated double sampling (CDS) method is used in conjunction with the output offset storage (OOS)
technology. The comparator's decision point in the suggested structure is independent of the input signal. The
input level-induced variation in the comparator offset is removed. The non-idealities from the column ADC and
the ramp generator are both corrected via a foreground calibration.
A two-step conversion procedure is used by the ADC. A coarse conversion and a fine conversion are the two
stages of the conversion process. Comparing this two-step method to conventional single-slope ADCs enables
faster conversion times.
The suggested ADC, designed and simulated on a 130nm CMOS process, achieves +0.76/−0.8 LSB for
differential non-linearity and +1.06/−0.84 LSB for integral non-linearity at 100 KS/s sampling frequency with
calibration. Also, there is an improvement in the effective number of bits (ENOB) from 4.66 bits to 11.25 bits.
With a power consumption of 72 μW, the single ADC has an active area of 7.5 × 775 μm2.