A 12-BIT COLUMN-PARALLEL TWO-STEP SINGLE-SLOPE ADC WITH A FOREGROUND CALIBRATION FOR CMOS IMAGE SENSORS

Abstract

A novel 12-bit column-parallel two-step single-slope (SS) analog-to-digital converter (ADC) for
high-speed CMOS image sensors. A CMOS image sensor, short for Complementary Metal-Oxide-
Semiconductor image sensor, is a tiny electronic device that plays a crucial role in capturing the images we see
on our digital cameras, smartphones, and various imaging devices. It acts as the "electronic eye" of these
devices, converting light into digital information we can process and view.Cooperating with the output offset
storage (OOS) technique, a new correlated double sampling (CDS) is adopted to reduce the non-uniformity in
column-level ADCs. In the proposed structure, the decision point of the comparator is independent of the input
signal. The variation of the comparator offset caused by the input level is eliminated. Through a foreground
calibration, the non-idealities from the ramp generator and the column ADC are both corrected.
The ADC uses a two-step conversion process. The conversion is split into two phases: a coarse
conversion and a fine conversion. This two-step approach allows for faster conversion times compared to
traditional single-slope ADCs.
Design and simulation in a 130nm CMOS process, the proposed ADC achieves the differential nonlinearity
(DNL) of +0.76/−0.8 LSB and the integral non-linearity (INL) of +1.06/−0.84 LSB at a sampling
frequency of 100 KS/s with the calibration. The effective number of bits (ENOB) is also improved from 4.66
bits to 11.25 bits. The single ADC occupies an active area of 7.5 × 775 μm2 and the power consumption is 72
μW.