Cascode Cross-Coupled Stage High Speed Dynamic Comparator

Abstract

This Project proposed a CMOS Three modelled comparator and its new version to enhance the speed and reduce the noise. When validate with conventional comparators this proposed comparator will enhance additional amplification structure, with this the efficiency of the proposed model will increase enormously, In proposed model an extra signal has been configured in the regeneration stage, in turn will enhance the speed of the proposed circuit will increase further. To validate the proposed model, using 45nm BSIM4 Model. By comparison, proposed model dictates that three stage circuits enhance speed by 34% and dwindles noise by several times. The proposed model has been validated through Mentor graphics 45nm BSIM4 Technology.