Optimized 4-Tap Fir Filter Using Braun Multiplier And Ripple Carry Adder

Abstract

This work presents the FPGA implementation of a finite impulse response (FIR) filter utilizing a Ripple Carry Adder (RCA) as the core addition unit. The design emphasizes simplicity, area efficiency, and functional reliability, making it suitable for cost-sensitive embedded DSP systems. Developed using Verilog HDL and tested on a Xilinx FPGA, the architecture demonstrates accurate frequency response, as confirmed by simulation results. While the RCA introduces a predictable delay, this is acceptable for low-speed applications, and the design benefits from ease of hardware implementation and straightforward debugging. Power and area analyses further highlight the practicality of this approach. The study also suggests that exploring faster adder architectures could enhance performance, positioning the RCA-based FIR filter as a baseline for future research in high-speed digital filtering.