Area And Power Efficient VLSI Architecture Of Approximate Multiplier Using Majority Logic . International Journal of Engineering and Science Research, [S. l.], v. 15, n. 1s, p. 594–603, 2025. Disponível em: https://www.ijesr.org/index.php/ijesr/article/view/694. Acesso em: 3 aug. 2025.