Area And Power Efficient VLSI Architecture Of Approximate Multiplier Using Majority Logic

Abstract

In this work, we present an approximate multiplier 
architecture that leverages a 6:3 compressor using 
majority gates, coupled with a Carry Look-Ahead 
Adder (CLA), and compare its performance to a 
existing multiplier using a Ripple Carry Adder (RCA) 
with the same 6:3 compressor. The primary aim of 
this study is to evaluate the efficiency, speed, and 
power consumption of the approximate multiplier 
designs. We demonstrate that the multiplier using a 
CLA achieves superior results in terms of reduced 
delay and enhanced overall performance compared 
to the RCA-based design. The CLA’s parallel carry 
propagation mechanism significantly minimizes the