DESIGN AND SIMULATION OF CRC ENCODER AND DECODER USING VHDL

Abstract

Traditionally, memory cells were the only circuitry susceptible to transient faults. The supporting
circuitries around the memory were assumed to be fault-free. Due to the increase in soft error rate in logic circuits,
the encoder and decoder circuitry around the memory blocks have become susceptible to soft errors as well and
must be protected. In this paper a new approach to design fault-secure encoder and decoder circuitry for memory
designs. The key novel contribution of this paper is identifying and defining a new class of error-correcting codes
whose redundancy makes the design of fault secure detectors(FSD) particularly simple. We further quantify the
importance of protecting encoder and decoder circuitry against transient errors, illustrating a scenario where the
system failure rate(FIT) is dominated by the failure rate of the encoder and decoder.
Prove that Euclidean Geometry Low-Density Parity-Check(EG-LDPC) codes have the fault secure detector
capability. Using some of the smaller EG-LDPC Codes, we can tolerate bit or nanowire defect rates of 10% and
fault rates of 10^-18 upsets, achieving a FIT rate at or below one for the entire memory system and a memory
density of10^11 bit/cm2 with nanowire pitch of 10nm for memory blocks of 10Mb or longer. Larger EG-LDPC
codes can achieve even higher reliability and lower area overhead.