Design Of Power And Area Efficient Approximate Multipliers

Abstract

Approximate computing can decrease the design 
complexity with an increase in performance of 
area, delay and power efficiency for error 
resilient applications. This brief deals with a new 
design approach for approximation of multipliers. 
The partial products of the multiplier are altered 
to introduce varying probability terms. Logic 
complexity of approximation is varied for the 
accumulation of altered partial products based on 
their probability. The proposed approximation is 
utilized in two variants of 8-bit multipliers and 
that proposed approximated dada multiplier 
achieve power saving, area and delay 
respectively, compared to an exact dada 
multiplier. 
Performance of the proposed 
multipliers is evaluated with an image processing 
application.