Advanced FIFO Structure For Router In Bi-Noc

Abstract

Network on chip (NoC) becomes a promising 
solution for intercommunication infrastructure in 
System on Chip (SoC) as traditional methods exhibit 
severe bottlenecks at intercommunication among 
processor elements. However, designing of NoC is 
majorly complex because of lot of issues raise in 
terms of performance metrics such as system 
scalability, latency, power consumption and signal 
integrity. This paper discussed issues of memory unit 
in router and thereafter, proposing advanced 
memory structure. To obtain efficient data transfer, 
FIFO buffers are implemented in distributed RAM 
and virtual channels for FPGA based NoC. An 
advanced FIFO based memory units are proposed in 
NoC router and the performance is evaluated in Bi
directional NoC (Bi-NoC). The major motivation of 
this paper is to reduce burden of router while 
improving FIFO internal structure. Toenhance the 
speed data transfer, Bi-NoC with a self-configurable 
intercommunication channel is proposed. The 
Simulations and synthesis results are proven 
guaranteed throughput, predictable latency, and fair 
network access highly provided when compared to 
recent works.