DEVELOPING A SHIFT REGISTER INCORPORATING PULSED LATCHES TO ENHANCE LOW POWER CONSUMPTION AND AREA EFFICIENCY

Abstract

Proposing a low-power and area-efficient shift register design using pulse latches, this project
offers an innovative approach to minimize both the area and energy consumption. By replacing flip-flops
with pulse latches, the design achieves reductions in both area and power consumption. Unlike
conventional designs relying on a single clock signal, this system employs a set of non-overlapping
delayed clock signals to address the timing issue between pulse latches effectively. By distributing the
latches among a small number of sub-shifter registers and employing a mechanism of temporary storage
latches, the shift register significantly reduces its dependence on clock signals. For the implementation, a
256-cycle shift register with pulse latches was designed using a 0.18μm CMOS process with VDD =
1.8V. The area footprint was minimized to 6600 sq. ft., while achieving a power consumption of 1.2mW
at a clock frequency of 100 MHz. Comparative analysis revealed that the proposed shift register design
could potentially save up to 37% of the required area and 44% of the required power compared to a
conventional flip-flop-based shift register. In essence, a shift register comprises a series of flip-flops or
pulse latches operating with the same clock signal, wherein the output of each element is connected to the
"data" input of the subsequent element. This configuration enables the circuit to shift the stored data by
one position upon each clock transition, thereby shifting in new data at the input and releasing the last bit
in the sequence. Additionally, shift registers can be designed with multiple stages to accommodate larger
data sets, enabling parallel operation for increased efficiency.